PhD in Computer Science

Low-latency and high bandwidth TCP/IP protocol processing through an integrated HW/SW approach

Academic year 2013/2014

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Course objectives

Abstract:

Ultra low-latency networking is critical in many domains, such as high frequency trading and high performance computing (HPC), and highly desirable in many others such as VoIP and on-line gaming. In closed systems - such as those found in HPC - Infiniband, iWARP or RoCE are common choices as system architects have the opportunity to choose the best host configurations and networking fabric. However, the vast majority of networks are built upon Ethernet with nodes exchanging data using the standard TCP/IP stack. On such networks, achieving ultra low-latency while maintaining compatibility with a standard TCP/IP stack is crucial.

To date, most efforts for low-latency packet transfers have focused on three main areas: (i) avoiding context switches, (ii) avoiding buffer copies, and (iii) off-loading protocol processing. We describes IBM PowerEN and its networking stack, showing that an integrated system design which treats Ethernet adapters as first class citizens that share the system bus with CPUs and memory, rather than as peripheral PCI Express attached devices, is a winning solution for achieving minimal latency. The presented work results in outstanding performance figures, including 1.30μs from wire to wire for UDP, usually the chosen protocol for latency sensitive applications, and excellent latency and bandwidth figures for the more complex TCP. 

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Note

The seminar will be held by (short bio):

Massimiliano Meneghin is a research engineer at IBM Dublin Lab. He got his PhD in computer science from the University of Pisa in 2010 with a study on a new optimisation theory for data parallel applications with stencils.  During his PhD, Massimiliano worked also on a communications library for the IBM Cell BE architecture and he started collaborating with the FastFlow project on lock free queue algorithms. 

In 2010, Massimiliano joined the IBM Research Dublin Lab, where he worked at the software stack for the IBM PowerEN architecture. He took part of the designed and developed an XML linux driver for the PowerEN XML accelerator and  a TCP/IP software stack for the PowerEN ethernet adapter. During the same period,  Massimiliano also worked on new lock free queue algorithms and the impact of a new PowerEN instruction on synchronisation mechanisms for multithreading applications. 

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